esp bug 1

Hard to explain - esp is a formal verilog tool. The problem was that it wouldn't properly end on $finish down certain branches. Here is the code:

module  test; 
reg     [1:0]   fred;
reg     [1:0]   fred_sym;
initial begin
        $esp_var(fred_sym);
        fred=fred_sym;

        // Don't allow this value
        if (fred===2'b01) $finish;

        // So how can it happen here?
        if (fred===2'b01) $esp_error("How did this happen?");
end
endmodule