finsim bug? 1

Finsim is a verilog compiler. Evidently it special cases registers that are 32 bits or bigger. This isn't noticeable until you try something wonky like a negative repeat. This isn't really a bug, it's undefined verilog behavior. Rats.

module top ();
// Timeout
initial #10 $finish;

reg	[31:0]	big_num;
initial begin
	big_num = -3;
	// This repeat executes 0 times
	repeat (big_num) #1 $write("repeat negative with big_num (32+ bits)\n");

reg	[30:0]	small_num;
initial begin
	small_num = -3;
	// This repeat executes many, many times (signed val of -3)
	repeat (small_num) #1 $write("repeat negative with small_num (<32 bits)\n");
I don't have access to IEEE.1364 (verilog standard), so I can't say for sure what it's supposed to do. In all fairness, it's probably undefined behavior, in which case this isn't entirely a bug, but I would argue that the behavior should be consistent.