finsim bug 2

Finsim is a verilog compiler.

I had a long case (that can't easily be shortened) where random numbers that were left shifted by a multiple of 32 would get weird behavior. In the end, I ran this:

  tmp1 and tmp2 are both defined as reg [106:0]

$write("comparing:\ntmp1: %h\ntmp2: %h\n\n",tmp1,tmp2);

if (tmp1[106:0] !== tmp2[106:0])
        $write("Bits [106:0] doesn't match\n");
if (tmp1[106:50] === tmp2[106:50])
        $write("but bits [106:50] DO match\n");
if (tmp1[49:0] === tmp2[49:0])
        $write("but bits [49:0] DO match\n");

// The top matches, the bottom matches, but the whole thing doesn't match!
if (tmp1[106:0] !== tmp2[106:0] &&
    tmp1[106:50] === tmp2[106:50] &&
    tmp1[49:0] === tmp2[49:0])
        $write("THIS IS AN IMPOSSIBLE STATE\n");
And managed to get the output: ----- Bits [106:0] doesn't match but bits [106:50] DO match but bits [49:0] DO match THIS IS AN IMPOSSIBLE STATE ----- Go figure. I never got a chance to root cause this bug - and the testcase is IP, so I can't reproduce it here, unfortunately. Maybe if finsim paid me as a verification engineer... ;)