# Modelsim Bug 1

Modelsim version: 6.2g
Operating System: Linux 2.6.8-3-686
Reported: 2007-03-30

Running the below case with coverage in MentorSim will cause a "missed expression" at:

Line 19: " | ((a | (~b)) & oporn);"

Clearly all input cases are covered. The Details window tells us that the following are missing in the truth table ('-' is don't care):

```    a
| b
| | op_and
| | | (a == b)
| | | | op_eq
| | | | | op_or
| | | | | | op_orn
| | | | | | | (((((a & b) & op_and) | ((a == b) & op_eq)) | ((a | b) & op_or)) | ((a | ~b) & op_orn))
| | | | | | | |
----------------
0 0 - 0 - - 0 0
```
This is a nonsense case because if a=0 and b=0, then a==b is 1.

The suggested fix is to use '~^' (xnor) instead of '=='

The test code:

```module tb ();

wire a, b;
wire out;
reg [1:0] op;
reg [1:0] ab;

assign op_and	= (op == 3'b000);
assign op_eq		= (op == 3'b001);
assign op_or		= (op == 3'b010);
assign op_orn	= (op == 3'b011);

assign a = ab;
assign b = ab;

assign out = ((a & b) & op_and)

| ((a == b) & op_eq)
//| ((a ~^ b) & op_eq)	// Use this line instead to fix

| ((a | b) & op_or)
| ((a | (~b)) & op_orn);

initial begin
op=0;
repeat (4) begin
ab=0;
repeat (4) begin
#1
\$write("op=%b a=%b b=%b -> %b\n",op,a,b,out);
ab=ab+1;
end
op=op+1;
end
end

endmodule

```