Modelsim Bug 2


Modelsim version: 6.2g
Operating System: Linux 2.6.8-3-686
Reported: 2007-04-09

Here's the mail sent to modelsim:

The coverage on and off pragmas are being finicky.

I have a testbench (that I don't want coverage data on) and a number
of blocks that it instantiates that I want coverage on.

I put '// coverage off' at the beginning of my testbench
and '// coverage on' at the end.

Evidently *sometimes* this turns off coverage for the instantiated
modules if they are instantiated inside of the '// coverage off' block,
but sometimes not.

This behavior should be consistent and reproducible.  My guess is
that it occurs according to the order that vsim processes the files
in which is perhaps quasi-random.

It took me a while to figure out why coverage wasn't working
in my second testbench which was essentially a clone of my
first testbench until I figured out this inconsistent behavior.


Here is a follow-up where I was able to somewhat reproduce the failure.

The testbench used to look like this:

---------------
// coverage off
..testbench code..
.. instantiate chip..
..testbench code..
// coverage on
---------------

The testbench code is generated for different blocks,
so each testbench is similar to the next.  I started
using a different block, and all the coverage disappeared.

Nothing would fix it until I did this (though this was
NOT required for the previous blocks):

---------------
// coverage off
..testbench code..
// coverage on
.. instantiate chip..
// coverage off
..testbench code..
// coverage on
---------------

Even then, many fiddling with recompilations was required.

I just played with it now and figured out some reproducible
behavior.

--------------------------------------------------
## testbench/chip NOT showing coverage

% vi testbench.v
## Take out ALL coverage pragmas
% vlog -cover sbceft testbench.v
% vsim -coverage -gui testbench -pli testbench_pli.sl &
## GUI now showing coverage in testbench.v ONLY

% vlog -cover sbceft -f chip.vc
## GUI STILL showing coverage in testbench.v ONLY

% rm -Rf work
% vlog -cover sbceft testbench.v
% vlog -cover sbceft -f chip.vc
% vsim -coverage -gui testbench -pli testbench_pli.sl &
## GUI NOW shows coverage in everything

% vi testbench.v
## Put coverage pragmas back in (all four of them)
% vlog -cover sbceft testbench.v
% vsim -coverage -gui testbench -pli testbench_pli.sl &
## GUI does one of two things:
## 1) All coverage is lost
## 2) Coverage is as hoped, only in the chip, not in the testbench
--------------------------------------------------

Once this happens it will stay in whichever state it chooses,
so if we have coverage at this point, we can edit the verilog,
run tests, etc,.. and we will keep seeing coverage.  Nothing
will make the coverage disappear at this point *unless* we
remove the inner coverage pragmas, then the coverage will
often suddenly disappear.

If we don't see coverage at this point, then nothing will bring
it back unless we go back to square one and remove all pragmas
and start over.

Somewhere there is some state that is clearly being maintained,
and I can't figure out where or what is causing this.  But the
inner pragmas point to some flakiness in determining whether
or not other verilog files should have compilation on, and that's
clearly incorrect.